As electronic technology progresses, integrated circuits (“IC”) such as logical devices and buses are becoming increasingly complex. Bus architectures, which typically include dedicated buses and common buses, are often integral part of such progress to achieve higher performance with less silicon. Typical common bus architecture consists of a single bus that is shared among multiple devices in a computer system or subsystem. A purpose of using the common bus is to simplify IC layout with relatively simple bus hardware.
A problem associated with a common bus is that some devices attached to the bus require longer bus access times to complete their transactions than others. For example, when there are multiple direct memory access (“DMA”) channels and all are trying to get access to a common bus, it is possible that one DMA channel can block other channels to create a bottleneck scenario. The bottleneck scenario can happen more often if latencies for getting data from different target modules are different in length.
A conventional approach to reduce the bottleneck scenario is to provide dedicated buses for devices that receive information with high latency. Dedicated buses typically increase hardware complexity and reduce overall bus performance. Another conventional approach to reduce the bottleneck scenario is to employ multiple common busses. For instance, when a first common bus is busy, requests may be redirected to a second common bus. The drawback for using multiple common buses is additional hardware and power usage.